1.
Sublect:
Openings for DWH PL
Contact:
akshita.verma@in.tesco.com
- Education: BE, Btech, ME, Mtech, MCA (full time)
- 5.5 – 7.5 years IT experience
- Experience in leading development projects with teams of 5 – 10 people in last 1yr.
- Min 1-2 yrs experience in Data warehousing or PL/SQL or ETL.
- Strong SQL skills
- Good communication and analytical skills
- Stability in previous jobs
- Has experience of working in/ leading development projects
Note:-
- The Opening is in Bangalore only.
- Kindly send across your updated resume.
2.
Subject:
Excellent Openings in Leading Investment Bank - Soniya from Staff Service Net
Contact:
Soniya Naik| 022-67135213
Staff Service Net
avani@ssn.co.in
Soniya here representing Staff Service Net and we are specialized in providing Software Professionals to the MNCs, to Domestic as well as International Clients.
I am forwarding the details of the requirements we are currently catering to. Kindly go through it and let me know whether you would be interested in the same.
Kindly go through the JD, the interviewer ask about what do you know about the profile
1) Company : A leading Investment Bank
Work Location: Mumbai
Skills : Core Java, Spring, Hibernate, with Strong Database
Experience : 6+ yrs
Skills : C++, VC++, Com Dcom, MFC
Experience : 4+ yrs
Skills : C++, stl, multithreading with strong database
Experience : 4+ yrs
Skills : Sybase/Sql with Unix (Development)
Experience : 3+ yrs
Skills : Sybase DBA
Experience : 5+ yrs
Skills : Unix, Sybase/Sql (Environment Analyst - Support)
Experience : 3+ yrs
Skills : Core Java, Springs frameworks, strong Database
Experience : 5+ yrs
===
Skills : Java, J2ee Client /Server Side Programming
Web Services, Object Model, Core Java, XML, Enterprise Java Beans, JMS.
design patterns, UML, OO concepts, Database Strong
Experience : 7+ yrs
Skills : Java, J2ee Tech lead UI
Develop GUI components using FLEX, JavaScript, HTML, and AJAX
UI design patterns, UML, OO concepts
Experience : 7+ yrs
Skills : J2EE Application Servers WebLogic
object oriented design (especially servlets, MDB and JMS)
Strong in Database, any operating system windows/unix
Proficient in Client/Server Side Development
Experience :3 to 10 yrs ( Your Profile would go for this requirement)
Skills : Core java, Spring and hibernate, Design patterns, Eclispse, RCP.
Experience : 3 to 8 yrs
Skills : J2ee, springs, struts, oops, multithreading,
Experience : 3 to 8 yrs
Skills : Unix, Shell Scripting, AWk, Sed.
Experience : 3 to 8 yrs
Skills : Unix, Sql (C++/Core java) Responsible for Release
Database Strong
Experience : 3 to 8 yrs
Request you let us know your interest in the same.
-----------------------------------------------------------------------------
Subject:
For eInfochips Limited
Contact:
Ashok Sharma
Talent HR Solutions
+91-11- 22561178, |+91-9811964222(M)
Email- ashok@talenthrs.net ;
ashok.talenthrs@gmail.com ;
Hi,
(Kindly see the Below given Requirements)
Wanted to apprise you of a great opportunity with a leading company based in Ahmedabad called eInfochips Limited at Ahmedabad .
www.einfochips.com
Details on the openings are given below . Pls review and let us know if you fit into the open positions and they are suitable to you .If you are interested , pls confirm immediately with your latest cv as the requirement is HOT and urgent. I also need the following dtls :
This info is a must as we shall forward your papers to the client along with this information :
Current Salary:-
Expected Salary:-
Communication Skills (Average,Good,Excellent)
Joining Time
Current employer / position / and location;
Total & relavant Exp in years & months -
Reasons for leaving you current job;
Location Preference Ahmedabad :-
Contact # for tele i/v or HR discussion (pls give mobile# , if avlbl)
Qualification : B.E./B.Tech,M.E/M.Tech (CS / EC / IC)
-: Hot Requirements :-
Position # Analog DFT
Location :- Ahmedabad
Exp. :- 3 - 5 yrs
Job Description
· Responsibilities include all aspects of the deployment and implementation of DFT: full scan, Memory BIST, JTAG, boundary scan, scan compression, high speed interface BIST, as well as other built in self test techniques as may be required from time to time.
· To interface with other groups within the company, including front end design engineering, physical design engineering group.
· Build and train a small team of DFT engineers.
· Assist in pre-sales situations for technical discussions with prospective customers requesting DFT services for large chips.
Requirements :-
· 3+ years of experience in DFT / test field.
· Strong understanding & hands-on experience with industry standard DFT techniques such as boundary scan , scan/ATPG/Fault simulation, memory BIST & repair, scan compression/BIST, BIST for high speed serial links.
· Strong hands-on DFT integration/tape-out of large chips with the logic design flow, RTL-implementation & verification, logic synthesis, logic equivalent checking, static timing analysis, & back end support for timing closure.
· Proficiency with Synopsys DFT toolset or Mentor Graphics tool set.
· Proficiency in programming/scripting : Perl, Tcl, make, Linux/Unix shell script.
- Proficiency in analyzing reports from DFT and STA tools.
- Good English language oral and written communications skills
Position # ASIC Manager
Location :- Ahmedabad
Exp. :- 8 - 15 yrs
Job Description:
· Defining and implementing SoC and module level functional verification environments using the latest advanced verification techniques, making use of high level verification languages and related methodologies
· Extensive Experience in languages like C++, System Verilog, e, Vera, Knowledge of eRM, VMM or OVM is required
· Proven track record of successfully completing the verification of complex ASIC's using high-level verification languages such as SystemVerilog or Specman with constrained random testing methodologies. Experience on managing and leading SoC/ASIC verification team for multiple ASIC projects.
· Manage the engineering teams in completing projects within time and budget parameters to meet contract requirements
· Effectively manage sub-contracted projects and issues
· Define project specifics, deliverables, and estimate scope, duration, and the required effort of proposed work
· Assure compatibility of resources, tools, platform; work with customers through acceptance of deliverables
· Work with Business Development and Technical Pre-Sales Teams on architecture, project feasibility, cost, schedule, deliverables, and requirements for Statement of Work and Proposal
· Conduct technical presentations to customers
· Effectively manage team members through coaching and mentoring, provide technical direction to team members on project issues, and provide guidance and career planning to team members
· Ensure customer satisfaction
· Build relationship with customers to further enhance the business potential
· Interface with account manager and sales team to gauge the project progress status
· Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes and recommend and implement new processes
Candidate Profile·
Minimum 8-15 years experience in a managing role in engineering
· Should be handling a team of atleast 10 people
· Engineering management skills demonstrated through successfully planning and managing multiple engineering projects and directing the design and troubleshooting of complex software or hardware
· Exp in ASIC, VLSI Design (both front & backend), Physical Design, FPGA
· BE/BTech/MTech/MS degree
· Excellent verbal and written English communication skills
Position # Backend / ASIC manager
Location :- Ahmedabad
Exp. :- 5+yrs
Desired total experience:
5+ years of direct relevant experience
Technical details:
(Must have the following skill sets)
Hands-on experience in the complete ASIC backend flow using Cadence SoCEncounter or Synopsys or Magma Tools. Experience in Cadence/Synopsys tools is preferred.
Experience of 3 or more ASIC tape-outs
Timing closure using PT
Floor planning, Power route, Clock Tree Synthesis, Global/Detail Route, Cross talk avoidance, signal integrity and EMIR analysis
DRC/LVS verification, antenna fixing.
Hard macro insertion
Desired skill sets:
Knowledge of Verilog and C (programming languages)
Good knowledge of the entire ASIC design flow from concept to silicon
Good knowledge of CMOS devices
Digital timing fundamentals
Scripting languages (Perl, Tcl/Tk, C-shell)
Physical design experience in 65-90nm technologies.
Mutli-Vdd flow
Timing closure for high speed interfaces like DDR2
Low power design techniques
Industry exposure:
65nm to 180nm designs using TSMC/UMC/CSC libraries
Deliverables for this person for the first 6 months:
Oversee the activities on one or more customer project(s)
Manage and motivate the Physical design team to deliver high quality output
Training the junior engineers
Recruit 5 engineers (2-senior and 3-junior)
Desired soft skills:
People management
Communication
Problem solving
Initiative
Team player
**********************
Company Profile :-
eInfochips Inc., based in Santa Clara, is a leading provider of cutting edge ASIC design and verification services, Embedded systems solutions and IP cores. Their capabilities extend from Specification to System, with knowledge on ASIC design & verification, physical design, board design and embedded firmware development. The company's India and US design centers have delivered SoC and Embedded solutions to a variety of customers thus increasing their cost-effectiveness, reducing their time-to-market and growing their market strength. A partial list of customers includes Gatelinx, TI, IDEO, Object Video,and Cisco. For additional information, please visit www.einfochips.com
Ahmedabad, July 11, 2005: eInfochips, a leading chip & systems design services firm with "spec-to-silicon-to-system" capabilities and Texas Instruments (TI) today announced an expansion of their effort to tap the growing demand for digital signal processing (DSP) expertise. eInfochips will ramp up the strength of its engineering team on TI's DSP platforms and will also expand its reach in Europe and Asia-Pacific to service TI customers in these markets
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Best regards,
Wednesday, February 11, 2009
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